1. Field of the Invention
The present invention generally relates to semiconductor memory devices and operating method therefor, and more particularly, to an increase of an access speed of a semiconductor memory device.
2. Description of the Background Art
FIG. 8 is a block diagram showing a structure of a conventional dynamic random access memory (hereinafter referred to as a dynamic RAM).
In a dynamic RAM 100 in FIG. 8, a memory array 1 includes a plurality of bit line pairs BL, a plurality of word lines WL crossing the plurality of bit line pairs BL and a plurality of dynamic type memory cells MC provided at the crossings thereof. Each of the bit line pairs BL is connected to a data bus DB through a N channel MOS transistors 31 and 32 constituting a transfer gate.
A /RAS buffer 2 receives an externally applied row address strobe signal /RAS to generate a control signal .phi..sub./RAS. A /CAS buffer 3 receives an externally applied column address strobe signal /CAS to generate a control signal .phi..sub./CAS. A /WE buffer 4 receives an externally applied write enable signal /WE to generate a control signal .phi..sub./WE.
An X address buffer 5 receives externally applied address signals A0-An, and generates an X address signal XA in response to the control signal .phi..sub./RAS. An X address decoder 6 selects any one of a plurality of word lines WL in response to the X address signal XA.
A Y address buffer 7 receives externally applied address signals A0-An, and generates a Y address signal YA in response to the control signals .phi..sub./RAS and .phi..sub./CAS. A Y address decoder 8 responds to the Y address signal YA to apply column selection signals C1 to Cm for selecting any one of a plurality of bit line pairs BL to the gates of transistors 31 and 32.
An ATD generating circuit 9 detects a transition of the Y address signal YA to generate a detection signal ATD. The detection signal ATD is a pulse signal. A signal generating circuit 10 responds to the detection signal ATD to generate an equalize signal EQ. A signal generating circuit 11 responds to the detection signal ATD to generate an amplifying circuit activation signal SE. A signal generating circuit 12 responds to the detection signal ATD to generate a Y address decoder activation signal DE.
A Din buffer 13 responds to the control signals .phi..sub./WE, .phi..sub./CAS and .phi..sub./RAS to apply an externally applied input data Din to the data bus DB. An equalizing circuit 14 responds to an activation signal EQ to equalize the potentials on the data bus DB. An amplifying circuit 15 responds to the activation signal SE to amplify the data on the data bus DB.
A signal generating circuit 16 responds to the control signals .phi..sub./CAS, .phi..sub./WE to generate an output circuit activation signal OE. An output circuit 17 responds to the activation signal OE to provide the data amplified by the amplifying circuit 15 as an output data Dout.
Next, a normal reading operation of the dynamic RAM shown in FIG. 8 will be described with reference to a signal waveform diagram of FIG. 9.
The X address XA is applied to the X address decoder 6 in response to the fall of the row address strobe signal /RAS, whereby any one of a plurality of word lines WL is selected. As a result, data are read from a plurality of memory cells MC connected to the selected word line WL to the corresponding bit line pairs BL, respectively.
When address signals A0-An change from the X address XA to the Y address YA1, the detection signal ATD rises to a logic high or "H" level. The equalize signal EQ rises to "H" in response to the rise of the detection signal ATD, whereby the equalizing circuit 14 is activated and the potentials on the data bus DB are equalized. At the same time, the activation signal DE rises to "H", whereby the Y address decoder 8 is activated.
After a prescribed period of time, the detection signal ATD falls to a logic low or "L" level. The equalize signal EQ falls to "L" in response to the fall of the detection signal ATD, whereby equalization of the data bus DB is completed.
The Y address decoder 8 raises any one of the column selection signals C1 to Cm to "H", whereby one bit line pair BL is selected and the transistors 31 and 32 corresponding thereto are turned on. As a result, data is read to the data bus DB from the selected bit line pair BL.
In addition, the activation signal SE rises to "H" in response to the fall of the detection signal ATD, whereby the amplifying circuit 15 is activated and the data on the data bus DB is amplified. Data amplified by the amplifying circuit 15 is applied to the output circuit 17 at a high speed. After data is applied to the output circuit 17, the activation signal DE and the activation signal SE fall to "L" in order to suppress an operation current.
When the address signals A0-An change from the Y address YA1 to a Y address YA2, the detection signal ATD rises to "H", whereby, similarly the potentials on the data bus DB are equalized by the equalizing circuit 14, then data read to the data bus DB is amplified by the amplifying circuit 15, and the amplified data is applied to the output circuit 17 at a high speed.
When the activation signal OE rises to "H", the output circuit 17 is activated to provide the output data Dout.
Next, static column mode operation of the dynamic RAM shown in FIG. 8 will be described with reference to the signal waveform diagram of FIG. 10.
In the static column mode, data is accessed as Y address changes. When the column address strobe signal /CAS is "L", data is provided.
First, the X address XA is applied to the X address decoder 6 in response to the fall of the row address strobe signal /RAS, whereby any one of a plurality of word lines WL is selected. Then, data is read from a plurality of memory cells MC connected to the selected word line WL to the corresponding bit line pairs BL, respectively.
When address signals A0-An change from the X address XA to the Y address YA1, the detection signal ATD rises to "H". An activation signal EQ rises to "H" in response to the rise of the detection signal ATD, whereby the equalizing circuit 14 is activated and the potentials on the data bus DB are equalized. Simultaneously, the activation signal DE rises to "H", whereby the Y address decoder 8 is activated.
The detection signal ATD falls to "L" after a prescribed period of time. The equalized signal EQ falls to "L" in response to the fall of the detection signal ATD, whereby the equalization of the data bus DB is completed.
The Y address decoder 8 raises any one of the column selection signals C1-Cm to "H", whereby one bit line pair BL is selected and the transistors 31 and 32 corresponding thereto are turned on. As a result, data of the Y address YA1 is read from the selected bit line pair BL to the data bus DB.
In addition, the activation signal SE rises to "H" in response to the fall of the detection signal ATD, whereby the amplifying circuit 15 is activated and data on the data bus DB is amplified. Data amplified by the amplifying circuit 15 is applied to the output circuit 17 at a high speed. The activation signals DE and SE fall to "L" a prescribed period of time after the rise, respectively.
When the activation signal OE rises to "H", the output circuit 17 is activated, whereby data of the address YA1 is provided as the output data Dout.
When address signals A0-An change from the Y address YA1 to the Y address YA2, the detection signal ATD rises to "H", whereby the potentials on the data bus DB are equalized by the equalizing circuit 14 and, then data of a Y address YA3 read to the data bus DB is amplified by the amplifying circuit 15. In this case, the output circuit 17 is activated and data in the Y address YA2 is provided as an output data Dout.
In addition, when address signals A0-An change from the Y address YA2 to the Y address YA3, the detection signal ATD rises to "H", whereby the potentials on the data bus DB are equalized by the equalizing circuit 14, and then data in the Y address YA3 read to the data bus DB is amplified by the amplifying circuit 15. In this case, the output circuit 17 is activated and data in the Y address YA3 is provided as the output data Dout.
Thus, data is sequentially provided in response to the transition of the Y address.
As described above, in a conventional dynamic RAM, the potentials on the data bus DB are equalized after the detection signal ATD rises to "H". The amplifying circuit 15 cannot be operated until the equalization of the data bus DB is completed so that the potentials on the data bus DB are made to be the same. Therefore, access time of data is made to be longer by the time required for the equalization.
In the static column mode, data cannot be provided by the output circuit 17 until data on the data bus DB is amplified by the amplifying circuit 15. Therefore, the access time and the cycle time cannot be shortened.